From: Tim Newsome <tim@sifive.com>
Date: Wed, 13 Jul 2016 20:26:09 +0000 (-0700)
Subject: Fix single step over csrw instructions. (#57)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75494f3abd1195fb66d6dbe7e6feefc487ac6333;p=riscv-isa-sim.git

Fix single step over csrw instructions. (#57)

csrw instructions instantly return if the PC isn't serialized. Take note
of this, and don't enter debug mode until the instruction we just
executed actually completed.
---

diff --git a/riscv/execute.cc b/riscv/execute.cc
index e2e72d6..20567af 100644
--- a/riscv/execute.cc
+++ b/riscv/execute.cc
@@ -97,18 +97,22 @@ void processor_t::step(size_t n)
         {
           if (unlikely(state.single_step == state.STEP_STEPPING)) {
             state.single_step = state.STEP_STEPPED;
-          } else if (unlikely(state.single_step == state.STEP_STEPPED)) {
-            state.single_step = state.STEP_NONE;
-            enter_debug_mode(DCSR_CAUSE_STEP);
-            // enter_debug_mode changed state.pc, so we can't just continue.
-            break;
           }
 
           insn_fetch_t fetch = mmu->load_insn(pc);
           if (debug && !state.serialized)
             disasm(fetch.insn);
           pc = execute_insn(this, pc, fetch);
+          bool serialize_before = (pc == PC_SERIALIZE_BEFORE);
+
           advance_pc();
+
+          if (unlikely(state.single_step == state.STEP_STEPPED) && !serialize_before) {
+            state.single_step = state.STEP_NONE;
+            enter_debug_mode(DCSR_CAUSE_STEP);
+            // enter_debug_mode changed state.pc, so we can't just continue.
+            break;
+          }
         }
       }
       else while (instret < n)