From: Jacob Lifshay Date: Sat, 13 May 2023 01:01:35 +0000 (-0700) Subject: fix bugs in fcvt* pseudocode X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=754da20cf5b7486ecd0c92d042c5dee7b8ca1411;p=libreriscv.git fix bugs in fcvt* pseudocode --- diff --git a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn index 9355c451b..203f37d99 100644 --- a/openpower/sv/int_fp_mv/moves_and_conversions.mdwn +++ b/openpower/sv/int_fp_mv/moves_and_conversions.mdwn @@ -480,11 +480,11 @@ Section 7.1 of the ECMAScript / JavaScript case(0): # Signed 32-bit range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(1): # Unsigned 32-bit range_min <- bfp_CONVERT_FROM_UI32(0) range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(2): # Signed 64-bit range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) @@ -560,6 +560,7 @@ Section 7.1 of the ECMAScript / JavaScript vx_flag <- vxsnan_flag | vxcvi_flag vex_flag <- FPSCR.VE & vx_flag + overflow <- 0 if vex_flag = 0 then RT <- result FPSCR.FPRF <- undefined @@ -639,11 +640,11 @@ Special Registers altered: case(0): # Signed 32-bit range_min <- bfp_CONVERT_FROM_SI32(0x8000_0000) range_max <- bfp_CONVERT_FROM_SI32(0x7FFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(1): # Unsigned 32-bit range_min <- bfp_CONVERT_FROM_UI32(0) range_max <- bfp_CONVERT_FROM_UI32(0xFFFF_FFFF) - js_mask <- 0xFFFF_FFFF + js_mask <- 0x0000_0000_FFFF_FFFF case(2): # Signed 64-bit range_min <- bfp_CONVERT_FROM_SI64(-0x8000_0000_0000_0000) range_max <- bfp_CONVERT_FROM_SI64(0x7FFF_FFFF_FFFF_FFFF) @@ -719,6 +720,7 @@ Special Registers altered: vx_flag <- vxsnan_flag | vxcvi_flag vex_flag <- FPSCR.VE & vx_flag + overflow <- 0 if vex_flag = 0 then RT <- result FPSCR.FPRF <- undefined