From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 5 Jun 2020 10:45:34 +0000 (+0100)
Subject: fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)
X-Git-Tag: div_pipeline~565
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=756a92619526c8704d149bb5996509f9cc08ea2d;p=soc.git

fix syntax errors and use correct FastRegs (SRR0/1 not SRR1/2)
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 28a68d18..1dc9b37f 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -220,6 +220,7 @@ class DecodeOut(Elaboratable):
     def elaborate(self, platform):
         m = Module()
         comb = m.d.comb
+        op = self.dec.op
 
         # select Register out field
         with m.Switch(self.sel_in):
diff --git a/src/soc/decoder/power_regspec_map.py b/src/soc/decoder/power_regspec_map.py
index 31d79a87..63435ae2 100644
--- a/src/soc/decoder/power_regspec_map.py
+++ b/src/soc/decoder/power_regspec_map.py
@@ -85,8 +85,8 @@ def regspec_decode(e, regfile, name):
         CTR = 1<<FastRegs.CTR
         LR = 1<<FastRegs.LR
         TAR = 1<<FastRegs.TAR
+        SRR0 = 1<<FastRegs.SRR0
         SRR1 = 1<<FastRegs.SRR1
-        SRR2 = 1<<FastRegs.SRR2
         if name in ['cia', 'nia']:
             return Const(1), PC, PC # TODO: detect read-conditions
         if name == 'msr':
diff --git a/src/soc/regfile/regfiles.py b/src/soc/regfile/regfiles.py
index ba732bed..a53ef5ab 100644
--- a/src/soc/regfile/regfiles.py
+++ b/src/soc/regfile/regfiles.py
@@ -58,8 +58,8 @@ class FastRegs(RegFileArray):
     CTR = 2
     LR = 3
     TAR = 4
-    SRR1 = 5
-    SRR2 = 6
+    SRR0 = 5
+    SRR1 = 6
     def __init__(self):
         super().__init__(64, 8)
         self.w_ports = [self.write_port("dest1"),