From: lkcl Date: Wed, 17 Aug 2022 02:32:37 +0000 (+0100) Subject: (no commit message) X-Git-Tag: opf_rfc_ls005_v1~847 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=756accd317b638053617a34d790e3ea5f527cc26;p=libreriscv.git --- diff --git a/openpower/sv/int_fp_mv.mdwn b/openpower/sv/int_fp_mv.mdwn index 275cb1824..d31198ded 100644 --- a/openpower/sv/int_fp_mv.mdwn +++ b/openpower/sv/int_fp_mv.mdwn @@ -117,12 +117,19 @@ but if followed up by `fishmv` an additional 16 bits of accuracy in the mantissa may be achieved. *IBM may consider it worthwhile to extend these two instructions to -v3.1 Prefixed (`pfmvis` and `pfishmv`). If so it is recommended that +v3.1 Prefixed (`pfmvis` and `pfishmv`: 8RR, imm0 extended). +If so it is recommended that `pfmvis` load a full FP32 immediate and `pfishmv` supplies the three high missing exponent bits (numbered 8 to 10) and the lower additional 29 mantissa bits (23 to 51) needed to construct a full FP64 immediate. Strictly speaking the sequence `fmvis fishmv pfishmv` achieves the -same effect in the same number of bytes, making `pfmvis` redundant.* +same effect in the same number of bytes as `pfmvis pfishmv`, +making `pfmvis` redundant.* + +Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv. +As fishmv is specifically intended to work in conjunction with fmvis +to provide additional accuracy, all bits other than those which +would have been set by a prior fmvis instruction are deliberately ignored. ## Load BF16 Immediate @@ -175,8 +182,6 @@ Special registers altered: None -Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv - ## Float Immediate Second-Half MV `fishmv FRS, D` @@ -211,11 +216,6 @@ Special registers altered: None -Just as Floating-point Load does not set FP Flags neither does fmvis or fishmv. -As this instruction is specifically intended to work in conjunction with fmvis -to provide additional accuracy, all bits in FRS other than those which -would have been set by an fmvis instruction are deliberately ignored - **This instruction performs a Read-Modify-Write.** *FRS is read, the additional 16 bit immediate inserted, and the result also written to FRS*