From: Sebastien Bourdeauducq Date: Sun, 11 Dec 2011 19:15:30 +0000 (+0100) Subject: bank: fix csrgen address decoder X-Git-Tag: 24jan2021_ls180~2099^2~1147 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7582b76406fdf36d391aea254a1a0d9b1ee3b2d6;p=litex.git bank: fix csrgen address decoder --- diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py index e605415b..460966b4 100644 --- a/migen/bank/csrgen.py +++ b/migen/bank/csrgen.py @@ -16,7 +16,7 @@ class Bank: comb = [] sync = [] - comb.append(a(self._sel, self.interface.a_i[12:] == f.Constant(self.address, f.BV(4)))) + comb.append(a(self._sel, self.interface.a_i[10:] == f.Constant(self.address, f.BV(4)))) nregs = len(self.description) nbits = f.BitsFor(nregs-1)