From: lkcl <lkcl@web>
Date: Sun, 5 Sep 2021 12:26:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~239
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75865651322b4b98e1350dee001952a788f3bba2;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index f31122c35..b07469b3e 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -208,6 +208,11 @@ The modes for `RA+RB` indexed version are slightly different:
 | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
 
+Vector Indexed Strided Mode is qualified as follows:
+
+    if mode = 0b01 and !RA.isvec and !RB.isvec:
+        svctx.ldstmode = elementstride
+
 A summary of the effect of Vectorisation of src or dest:
  
      imm(RA)  RT.v   RA.v   no stride allowed