From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Apr 2023 17:08:04 +0000 (+0100)
Subject: no, fdmadd(s) is definitely not the same as fmadd(s)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=759322bfe0478197a1cf3ea708a4444809054598;p=libreriscv.git

no, fdmadd(s) is definitely not the same as fmadd(s)
---

diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index 42c85c01f..1a17e9cdb 100644
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -144,9 +144,19 @@ Pseudo-code:
 
 ```
     FRS <- FPADD32(FRT, FRB)
-    FRT <- FPMULADD32(FRT, FRA, FRB, 1, -1)
+    sub <- FPSUB32(FRT, FRB)
+    FRT <- FPMUL32(FRA, sub)
 ```
 
+The two IEEE754-FP32 operations
+
+```
+    FRS <- [(FRT) + (FRB)]
+    FRT <- [(FRT) - (FRB)] * (FRA)
+```
+
+are simultaneously performed.
+
 The Floating-Point operand in register FRT is added to the floating-point
 operand in register FRB and the result stored in FRS.
 
@@ -156,9 +166,10 @@ FRB is subtracted from the floating-point operand in register FRT and
 the result then multiplied by FRA to create an intermediate result that
 is stored in FRT.
 
-The add into FRS is treated exactly as `fadd`.  The creation of the
-result FRT is exact!y that of `fmsub`.  The creation of FRS and FRT are
-treated as parallel independent operations which occur at the same time.
+The add into FRS is treated exactly as `fadds`.  The creation of the
+result FRT is **not** the same as that of `fmsubs`.
+The creation of FRS and FRT are treated as parallel independent operations
+which occur at the same time.
 
 Note that if Rc=1 an Illegal Instruction is raised.  Rc=1 is `RESERVED`
 
@@ -256,9 +267,19 @@ Pseudo-code:
 
 ```
     FRS <- FPADD64(FRT, FRB)
-    FRT <- FPMULADD64(FRT, FRA, FRB, 1, -1)
+    sub <- FPSUB64(FRT, FRB)
+    FRT <- FPMUL64(FRA, sub)
 ```
 
+The two IEEE754-FP64 operations
+
+```
+    FRS <- [(FRT) + (FRB)]
+    FRT <- [(FRT) - (FRB)] * (FRA)
+```
+
+are simultaneously performed.
+
 The Floating-Point operand in register FRT is added to the floating-point
 operand in register FRB and the result stored in FRS.
 
@@ -269,8 +290,9 @@ the result then multiplied by FRA to create an intermediate result that
 is stored in FRT.
 
 The add into FRS is treated exactly as `fadd`.  The creation of the
-result FRT is exact!y that of `fmsub`.  The creation of FRS and FRT are
-treated as parallel independent operations which occur at the same time.
+result FRT is **not** the same as that of `fmsub`.
+The creation of FRS and FRT are treated as parallel independent operations
+which occur at the same time.
 
 Note that if Rc=1 an Illegal Instruction is raised.  Rc=1 is `RESERVED`