From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 30 May 2020 13:21:32 +0000 (+0200)
Subject: wishbone/wishbone2csr: use wishbone.sel on CSR write.
X-Git-Tag: 24jan2021_ls180~253
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=759367752caf21475b57d468a442635a87ac273b;p=litex.git

wishbone/wishbone2csr: use wishbone.sel on CSR write.

CSR write is only done if wishbone.sel != 0. This should avoid the need for 64-bit
CSR alignment on 64-bit CPUs since a 64-bit Wishbone write access targeting only the
32-bit LSB or MSB will be splitted in 2x32-bit accesses: one with sel=0xf, one with sel=0.
---

diff --git a/litex/soc/interconnect/wishbone.py b/litex/soc/interconnect/wishbone.py
index be2f9f8d..75ed6f64 100644
--- a/litex/soc/interconnect/wishbone.py
+++ b/litex/soc/interconnect/wishbone.py
@@ -387,7 +387,7 @@ class Wishbone2CSR(Module):
         fsm.act("WRITE-READ",
             If(self.wishbone.cyc & self.wishbone.stb,
                 self.csr.adr.eq(self.wishbone.adr),
-                self.csr.we.eq(self.wishbone.we),
+                self.csr.we.eq(self.wishbone.we & (self.wishbone.sel != 0)),
                 NextState("ACK")
             )
         )