From: Marek Olšák <marek.olsak@amd.com>
Date: Thu, 17 Aug 2017 21:35:36 +0000 (+0200)
Subject: ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=759526813be137f7f139d6b4e56c5afeb8ba53c9;p=mesa.git

ac/surface/gfx9: don't allow DCC for the smallest mipmap levels

This fixes garbage there if we don't flush TC L2 after rendering.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
---

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 610071a956f..4edefc7c40a 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -908,6 +908,23 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
 			surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
 			surf->dcc_size = dout.dccRamSize;
 			surf->dcc_alignment = dout.dccRamBaseAlign;
+			surf->num_dcc_levels = in->numMipLevels;
+
+			/* Disable DCC for the smallest levels. It seems to be
+			 * required for DCC readability between CB and shaders
+			 * when TC L2 isn't flushed. This was guessed.
+			 *
+			 * Alternative solutions that also work but are worse:
+			 * - Disable DCC.
+			 * - Flush TC L2 after rendering.
+			 */
+			for (unsigned i = 1; i < in->numMipLevels; i++) {
+				if (mip_info[i].pitch *
+				    mip_info[i].height * surf->bpe < 1024) {
+					surf->num_dcc_levels = i;
+					break;
+				}
+			}
 		}
 
 		/* FMASK */
@@ -1061,6 +1078,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
 	surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
 
+	surf->num_dcc_levels = 0;
 	surf->surf_size = 0;
 	surf->dcc_size = 0;
 	surf->htile_size = 0;
@@ -1087,7 +1105,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	}
 
 	surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
-	surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
 
 	switch (surf->u.gfx9.surf.swizzle_mode) {
 		/* S = standard. */