From: Anatoly Sokolov Date: Thu, 15 Dec 2011 14:43:02 +0000 (+0400) Subject: arm.h (REGISTER_MOVE_COST, [...]): Remove. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7598036b5a94ff138f7ae9a007b385d1b6000afd;p=gcc.git arm.h (REGISTER_MOVE_COST, [...]): Remove. * config/arm/arm.h (REGISTER_MOVE_COST, MEMORY_MOVE_COST): Remove. * config/arm/arm.c (arm_memory_move_cost, arm_register_move_cost): New functions. (TARGET_REGISTER_MOVE_COST, TARGET_MEMORY_MOVE_COST): Define. From-SVN: r182369 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cdfac22d83f..3357e8fa806 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2011-12-15 Anatoly Sokolov + + * config/arm/arm.h (REGISTER_MOVE_COST, MEMORY_MOVE_COST): Remove. + * config/arm/arm.c (arm_memory_move_cost, arm_register_move_cost): + New functions. + (TARGET_REGISTER_MOVE_COST, TARGET_MEMORY_MOVE_COST): Define. + 2011-12-15 Richard Guenther PR lto/51564 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 65b4e9d58ae..3d3c4523c75 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -164,6 +164,8 @@ static bool arm_xscale_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool static bool arm_9e_rtx_costs (rtx, enum rtx_code, enum rtx_code, int *, bool); static bool arm_rtx_costs (rtx, int, int, int, int *, bool); static int arm_address_cost (rtx, bool); +static int arm_register_move_cost (enum machine_mode, reg_class_t, reg_class_t); +static int arm_memory_move_cost (enum machine_mode, reg_class_t, bool); static bool arm_memory_load_p (rtx); static bool arm_cirrus_insn_p (rtx); static void cirrus_reorg (rtx); @@ -363,6 +365,12 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST arm_adjust_cost +#undef TARGET_REGISTER_MOVE_COST +#define TARGET_REGISTER_MOVE_COST arm_register_move_cost + +#undef TARGET_MEMORY_MOVE_COST +#define TARGET_MEMORY_MOVE_COST arm_memory_move_cost + #undef TARGET_ENCODE_SECTION_INFO #ifdef ARM_PE #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info @@ -8484,6 +8492,63 @@ fa726te_sched_adjust_cost (rtx insn, rtx link, rtx dep, int * cost) return true; } +/* Implement TARGET_REGISTER_MOVE_COST. + + Moves between FPA_REGS and GENERAL_REGS are two memory insns. + Moves between VFP_REGS and GENERAL_REGS are a single insn, but + it is typically more expensive than a single memory access. We set + the cost to less than two memory accesses so that floating + point to integer conversion does not go through memory. */ + +int +arm_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, + reg_class_t from, reg_class_t to) +{ + if (TARGET_32BIT) + { + if ((from == FPA_REGS && to != FPA_REGS) + || (from != FPA_REGS && to == FPA_REGS)) + return 20; + else if ((IS_VFP_CLASS (from) && !IS_VFP_CLASS (to)) + || (!IS_VFP_CLASS (from) && IS_VFP_CLASS (to))) + return 15; + else if ((from == IWMMXT_REGS && to != IWMMXT_REGS) + || (from != IWMMXT_REGS && to == IWMMXT_REGS)) + return 4; + else if (from == IWMMXT_GR_REGS || to == IWMMXT_GR_REGS) + return 20; + else if ((from == CIRRUS_REGS && to != CIRRUS_REGS) + || (from != CIRRUS_REGS && to == CIRRUS_REGS)) + return 20; + else + return 2; + } + else + { + if (from == HI_REGS || to == HI_REGS) + return 4; + else + return 2; + } +} + +/* Implement TARGET_MEMORY_MOVE_COST. */ + +int +arm_memory_move_cost (enum machine_mode mode, reg_class_t rclass, + bool in ATTRIBUTE_UNUSED) +{ + if (TARGET_32BIT) + return 10; + else + { + if (GET_MODE_SIZE (mode) < 4) + return 8; + else + return ((2 * GET_MODE_SIZE (mode)) * (rclass == LO_REGS ? 1 : 2)); + } +} + /* This function implements the target macro TARGET_SCHED_ADJUST_COST. It corrects the value of COST based on the relationship between INSN and DEP through the dependence LINK. It returns the new diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8a9ed1f510b..5a781256b20 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -1281,26 +1281,6 @@ do { \ /* If defined, gives a class of registers that cannot be used as the operand of a SUBREG that changes the mode of the object illegally. */ - -/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. - Moves between VFP_REGS and GENERAL_REGS are a single insn, but - it is typically more expensive than a single memory access. We set - the cost to less than two memory accesses so that floating - point to integer conversion does not go through memory. */ -#define REGISTER_MOVE_COST(MODE, FROM, TO) \ - (TARGET_32BIT ? \ - ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ - (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ - IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ - !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ - (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ - (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ - (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ - (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ - (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ - 2) \ - : \ - ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) /* Stack layout; function entry, exit and calling. */ @@ -1953,12 +1933,6 @@ typedef struct ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ || (X) == arg_pointer_rtx) -/* Moves to and from memory are quite expensive */ -#define MEMORY_MOVE_COST(M, CLASS, IN) \ - (TARGET_32BIT ? 10 : \ - ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ - * (CLASS == LO_REGS ? 1 : 2))) - /* Try to generate sequences that don't involve branches, we can then use conditional instructions */ #define BRANCH_COST(speed_p, predictable_p) \