From: Jacob Lifshay Date: Fri, 19 Jan 2024 08:38:02 +0000 (-0800) Subject: add WIP 256-bit add frame X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=759c93b3e344284c2afc873aa4a60a17e86ef184;p=libreriscv.git add WIP 256-bit add frame --- diff --git a/conferences/fosdem2024/fosdem2024_bigint/bigint-add-pipe.dia b/conferences/fosdem2024/fosdem2024_bigint/bigint-add-pipe.dia new file mode 100644 index 000000000..3ef1a3f41 --- /dev/null +++ b/conferences/fosdem2024/fosdem2024_bigint/bigint-add-pipe.dia @@ -0,0 +1,458 @@ + + + + + + + + + + + + + #Letter# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ## + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #64-bit +Adder# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #64-bit +Adder# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #64-bit +Adder# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #64-bit +Adder# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + #256-bit SIMD +Adder# + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex index 8e51dbb11..832a88430 100644 --- a/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex +++ b/conferences/fosdem2024/fosdem2024_bigint/fosdem2024_bigint.tex @@ -45,7 +45,7 @@ add r5, r17, r12 \begin{frame}[fragile] \frametitle{Big-Integer Addition on SVP64} - How can we use SVP64 to add 192-bit integers? + How can we use SVP64 to add 256-bit integers? \pause \begin{semiverbatim} setvl 0, 0, 4, 0, 1, 1 # makes stuff run 4 times @@ -61,6 +61,17 @@ adde r6, r6, r11 \end{semiverbatim} \end{frame} +\begin{frame} + \frametitle{Big-Integer Addition on an example CPU} + Disclaimer: + SVP64 is designed for everything from tiny to big and fast CPUs, this example only shows a hypothetical big and fast CPU design +\end{frame} + +\begin{frame} + \frametitle{Big-Integer Addition on an example CPU} + \input{bigint-add-pipe.dia-tex} +\end{frame} + \begin{frame} \input{test.dia-tex} \end{frame}