From: Peter Bergner <bergner@vnet.ibm.com>
Date: Mon, 5 Mar 2018 15:52:11 +0000 (-0600)
Subject: re PR target/84264 (ICE in rs6000_emit_le_vsx_store, at config/rs6000/rs6000.c:10367... 
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75a741e87be51079ae6babbd7a8828a9b57dca79;p=gcc.git

re PR target/84264 (ICE in rs6000_emit_le_vsx_store, at config/rs6000/rs6000.c:10367 starting with r256656)

gcc/
	PR target/84264
	* config/rs6000/vector.md (mov<mode>): Disallow altivec memory operands.

gcc/testsuite/
	PR target/84264
	* g++.dg/pr84264.C: New test.

From-SVN: r258251
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index c52325615ba..723e718baa1 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-05  Peter Bergner  <bergner@vnet.ibm.com>
+
+	PR target/84264
+	* config/rs6000/vector.md (mov<mode>): Disallow altivec memory operands.
+
 2018-03-05  Richard Biener  <rguenther@suse.de>
 
 	PR tree-optimization/84486
diff --git a/gcc/config/rs6000/vector.md b/gcc/config/rs6000/vector.md
index 6e2576ee1d8..d27079bf129 100644
--- a/gcc/config/rs6000/vector.md
+++ b/gcc/config/rs6000/vector.md
@@ -132,12 +132,19 @@
 	  && !vlogical_operand (operands[1], <MODE>mode))
 	operands[1] = force_reg (<MODE>mode, operands[1]);
     }
+  /* When generating load/store instructions to/from VSX registers on
+     pre-power9 hardware in little endian mode, we need to emit register
+     permute instructions to byte swap the contents, since the VSX load/store
+     instructions do not include a byte swap as part of their operation.
+     Altivec loads and stores have no such problem, so we skip them below.  */
   if (!BYTES_BIG_ENDIAN
       && VECTOR_MEM_VSX_P (<MODE>mode)
       && !TARGET_P9_VECTOR
       && !gpr_or_gpr_p (operands[0], operands[1])
-      && (memory_operand (operands[0], <MODE>mode)
-          ^ memory_operand (operands[1], <MODE>mode)))
+      && ((memory_operand (operands[0], <MODE>mode)
+	   && !altivec_indexed_or_indirect_operand(operands[0], <MODE>mode))
+	  ^ (memory_operand (operands[1], <MODE>mode)
+	     && !altivec_indexed_or_indirect_operand(operands[1], <MODE>mode))))
     {
       rs6000_emit_le_vsx_move (operands[0], operands[1], <MODE>mode);
       DONE;
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 44543c31f0f..70bce764b06 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2018-03-05  Peter Bergner  <bergner@vnet.ibm.com>
+
+	PR target/84264
+	* g++.dg/pr84264.C: New test.
+
 2018-03-05  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/84618
diff --git a/gcc/testsuite/g++.dg/pr84264.C b/gcc/testsuite/g++.dg/pr84264.C
new file mode 100644
index 00000000000..4f8a77d8ac4
--- /dev/null
+++ b/gcc/testsuite/g++.dg/pr84264.C
@@ -0,0 +1,15 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-options "-w -O1 -fstack-protector-strong" } */
+
+void _setjmp ();
+void a (unsigned long *);
+void
+b (void)
+{
+  for (;;)
+    {
+      _setjmp ();
+      unsigned long args[9]{};
+      a (args);
+    }
+}