From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 23 Dec 2019 22:22:13 +0000 (-0800)
Subject: Fix CEA/CEB check
X-Git-Tag: working-ls180~902^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75acaff6f5416137fdf515bda5c214ccc228df98;p=yosys.git

Fix CEA/CEB check
---

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 1116afd41..9fdefff31 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -257,7 +257,7 @@ code argQ clock AREG
 					else if (param(prev, \AREG, 2) == 2)
 						CEA = \CEA1;
 					else log_abort();
-					if (!dffcemux && port(prev, CEA, State::S0) != State::S0)
+					if (!dffcemux && port(prev, CEA, State::S0) != State::S1)
 						goto reject_AREG;
 					if (dffcemux && port(dffcemux, \S) != port(prev, CEA, State::S0))
 						goto reject_AREG;
@@ -303,7 +303,7 @@ code argQ clock BREG
 						else log_abort();
 					}
 					else log_abort();
-					if (!dffcemux && port(prev, CEB, State::S0) != State::S0)
+					if (!dffcemux && port(prev, CEB, State::S0) != State::S1)
 						goto reject_BREG;
 					if (dffcemux && port(dffcemux, \S) != port(prev, CEB, State::S0))
 						goto reject_BREG;