From: lkcl <lkcl@web>
Date: Thu, 20 Apr 2023 23:58:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75afbad21a3c81301f614fbcb44234f963d12a89;p=libreriscv.git

---

diff --git a/openpower/sv/normal.mdwn b/openpower/sv/normal.mdwn
index c9d060668..8e3a539a6 100644
--- a/openpower/sv/normal.mdwn
+++ b/openpower/sv/normal.mdwn
@@ -150,7 +150,8 @@ Easy examples include Reduction on Logical OR or AND operations.*
 **Horizontal Parallelism Hint**
 
 `SVSTATE.hphint` declares to hardware that groups of elements up to this
-size are 100% independent.  With Reduction literally creating Dependency
+size are 100% independent (free of all Hazards inter-element but not inter-group).
+With Reduction literally creating Dependency
 Hazards on every element-level sub-instruction it is pretty clear that setting
 `hphint` *at all* would cause data corruption.  However `sv.add *r0, *r4, *r0`
 for example clearly leaves room for four parallel elements. Programmers must