From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 14 Apr 2020 17:43:05 +0000 (-0700)
Subject: design: do not delete when iterating over Design::modules() directly
X-Git-Tag: working-ls180~632^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75bb2c8c2472f4f09c556c09ae0ac3fb6a70d41a;p=yosys.git

design: do not delete when iterating over Design::modules() directly
---

diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc
index 4612760cc..8861182aa 100644
--- a/passes/cmds/design.cc
+++ b/passes/cmds/design.cc
@@ -340,7 +340,7 @@ struct DesignPass : public Pass {
 
 		if (reset_mode || !load_name.empty() || push_mode || pop_mode)
 		{
-			for (auto mod : design->modules())
+			for (auto mod : design->modules().to_vector())
 				design->remove(mod);
 
 			design->selection_stack.clear();