From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 27 May 2019 19:22:05 +0000 (-0700)
Subject: Parse without wideports
X-Git-Tag: working-ls180~1208^2~266
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75bd41eaeb43ec7a25f0b27ff0cdf3be361446f1;p=yosys.git

Parse without wideports
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index acbab959e..a2948548d 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -538,7 +538,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 		//parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
 		buffer = stringf("%s/%s", tempdir_name.c_str(), "input.sym");
 		log_assert(!design->module("$__abc9__"));
-		AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
+		AigerReader reader(design, ifs, "$__abc9__", "" /* clk_name */, buffer.c_str() /* map_filename */, false /* wideports */);
 		reader.parse_xaiger();
 
 		ifs.close();