From: Luke Kenneth Casson Leighton Date: Fri, 3 Sep 2021 07:13:14 +0000 (+0100) Subject: another batch of ready/valid i/o prefix-suffix swaps X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75bdc1747f32a4fb6cf848ed8b5c68ef2f683f4c;p=soc.git another batch of ready/valid i/o prefix-suffix swaps --- diff --git a/src/soc/fu/branch/test/test_pipe_caller.py b/src/soc/fu/branch/test/test_pipe_caller.py index 0c5b3b95..0b701ae8 100644 --- a/src/soc/fu/branch/test/test_pipe_caller.py +++ b/src/soc/fu/branch/test/test_pipe_caller.py @@ -74,8 +74,8 @@ class TestRunner(unittest.TestCase): m.submodules.branch = branch = BranchBasePipe(pspec) comb += branch.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) - comb += branch.p.valid_i.eq(1) - comb += branch.n.ready_i.eq(1) + comb += branch.p.i_valid.eq(1) + comb += branch.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/fu/compunits/formal/proof_fu.py b/src/soc/fu/compunits/formal/proof_fu.py index 06437df0..9ec497fa 100644 --- a/src/soc/fu/compunits/formal/proof_fu.py +++ b/src/soc/fu/compunits/formal/proof_fu.py @@ -114,12 +114,12 @@ class Driver(Elaboratable): alu_temp = Signal(16) write_req_valid = Signal(reset=0) with m.If(~Past(go_die) & Past(busy)): - with m.If(Rose(dut.alu.n.valid_o)): + with m.If(Rose(dut.alu.n.o_valid)): sync += alu_temp.eq(dut.alu.o) sync += write_req_valid.eq(1) # write_req_valid should only be high once the alu finishes - with m.If(~write_req_valid & ~dut.alu.n.valid_o): + with m.If(~write_req_valid & ~dut.alu.n.o_valid): comb += Assert(wr_rel == 0) # Property 6: Write request release is held up if shadow_n @@ -218,7 +218,7 @@ class FUTestCase(FHDLTestCase): 'oper_i_None__insn_type', 'i1[15:0]', 'i_valid', 'o_ready']), ('next port', 'out', [ - 'alu_o[15:0]', 'valid_o', 'ready_i'])])] + 'alu_o[15:0]', 'o_valid', 'i_ready'])])] write_gtkw('test_fu_formal_bmc.gtkw', os.path.dirname(__file__) + diff --git a/src/soc/fu/mmu/test/test_non_production_core.py b/src/soc/fu/mmu/test/test_non_production_core.py index 5a77a455..dc7d5c62 100644 --- a/src/soc/fu/mmu/test/test_non_production_core.py +++ b/src/soc/fu/mmu/test/test_non_production_core.py @@ -102,11 +102,11 @@ class TestRunner(unittest.TestCase): fsm = core.fus.fus["mmu0"].alu - vld = yield fsm.n.valid_o + vld = yield fsm.n.o_valid while not vld: yield if debughang: print("not valid -- hang") - vld = yield fsm.n.valid_o + vld = yield fsm.n.o_valid if debughang==2: vld=1 yield diff --git a/src/soc/fu/mmu/test/test_pipe_caller.py b/src/soc/fu/mmu/test/test_pipe_caller.py index 10c4b048..0bb9f4f9 100644 --- a/src/soc/fu/mmu/test/test_pipe_caller.py +++ b/src/soc/fu/mmu/test/test_pipe_caller.py @@ -189,13 +189,13 @@ class TestRunner(unittest.TestCase): index = pc//4 print("pc after %08x" % (pc)) - vld = yield fsm.n.valid_o #fsm + vld = yield fsm.n.o_valid #fsm while not vld: yield if debughang: print("not valid -- hang") return - vld = yield fsm.n.valid_o + vld = yield fsm.n.o_valid if debughang==2: vld=1 yield @@ -225,8 +225,8 @@ class TestRunner(unittest.TestCase): #FIXME connect fsm inputs comb += fsm.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) - comb += fsm.p.valid_i.eq(1) - comb += fsm.n.ready_i.eq(1) + comb += fsm.p.i_valid.eq(1) + comb += fsm.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/fu/spr/test/test_pipe_caller.py b/src/soc/fu/spr/test/test_pipe_caller.py index fbe2314d..d6aa34ea 100644 --- a/src/soc/fu/spr/test/test_pipe_caller.py +++ b/src/soc/fu/spr/test/test_pipe_caller.py @@ -122,10 +122,10 @@ class TestRunner(unittest.TestCase): index = pc//4 print("pc after %08x" % (pc)) - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid while not vld: yield - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid yield yield from self.check_alu_outputs(alu, pdecode2, sim, code) @@ -143,8 +143,8 @@ class TestRunner(unittest.TestCase): m.submodules.alu = alu = SPRBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) - comb += alu.p.valid_i.eq(1) - comb += alu.n.ready_i.eq(1) + comb += alu.p.i_valid.eq(1) + comb += alu.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) diff --git a/src/soc/fu/trap/test/test_pipe_caller.py b/src/soc/fu/trap/test/test_pipe_caller.py index 71ed8277..a634bc05 100644 --- a/src/soc/fu/trap/test/test_pipe_caller.py +++ b/src/soc/fu/trap/test/test_pipe_caller.py @@ -91,8 +91,8 @@ class TestRunner(unittest.TestCase): m.submodules.alu = alu = TrapBasePipe(pspec) comb += alu.p.i_data.ctx.op.eq_from_execute1(pdecode2.do) - comb += alu.p.valid_i.eq(1) - comb += alu.n.ready_i.eq(1) + comb += alu.p.i_valid.eq(1) + comb += alu.n.i_ready.eq(1) comb += pdecode2.dec.raw_opcode_in.eq(instruction) sim = Simulator(m) @@ -142,10 +142,10 @@ class TestRunner(unittest.TestCase): msr = sim.msr.value print("msr after %08x" % (msr)) - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid while not vld: yield - vld = yield alu.n.valid_o + vld = yield alu.n.o_valid yield yield from self.check_alu_outputs(alu, pdecode2,