From: Albert Ou <albert@sifive.com>
Date: Tue, 2 May 2017 19:35:34 +0000 (-0700)
Subject: spi: Fix off-by-one error in calculating cycles per data frame
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75d6a7c6eac209a32ecf2fc8d1b8cfc68450107d;p=sifive-blocks.git

spi: Fix off-by-one error in calculating cycles per data frame

Issue: Configuring the frame length to certain values causes incorrect
operation.

Symptoms: Certain frame lengths result in the master sending one extra
clock pulse.  The slave device may then become desynchronized.

Workaround: The following frame lengths are supported and can be used.
Do not use other frame lengths.
	* Serial mode: 0, 2, 4, 6, 8
	* Dual mode:   0, 1, 3, 5, 7, 8
	* Quad mode:   0, 1, 2, 3, 5, 6, 7, 8
---

diff --git a/src/main/scala/devices/spi/SPIFIFO.scala b/src/main/scala/devices/spi/SPIFIFO.scala
index a322a1b..5bc6e82 100644
--- a/src/main/scala/devices/spi/SPIFIFO.scala
+++ b/src/main/scala/devices/spi/SPIFIFO.scala
@@ -41,7 +41,7 @@ class SPIFIFO(c: SPIParamsBase) extends Module {
 
   val proto = SPIProtocol.decode(io.link.fmt.proto).zipWithIndex
   val cnt_quot = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len >> i) })
-  val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (io.ctrl.fmt.len(i, 0).orR) })
+  val cnt_rmdr = Mux1H(proto.map { case (s, i) => s -> (if (i > 0) io.ctrl.fmt.len(i-1, 0).orR else UInt(0)) })
   io.link.fmt <> io.ctrl.fmt
   io.link.cnt := cnt_quot + cnt_rmdr