From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 4 Nov 2020 15:26:35 +0000 (+0000)
Subject: update FPGA connector images
X-Git-Tag: convert-csv-opcode-to-binary~1866
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75d80fbf2b12ea3ff00ef85e7b10a136251f467b;p=libreriscv.git

update FPGA connector images
---

diff --git a/HDL_workflow/2020-11-03_13-22.png b/HDL_workflow/2020-11-03_13-22.png
index 1eb99708e..ac3732f69 100644
Binary files a/HDL_workflow/2020-11-03_13-22.png and b/HDL_workflow/2020-11-03_13-22.png differ
diff --git a/HDL_workflow/versa_ecp5_x3_connector.jpg b/HDL_workflow/versa_ecp5_x3_connector.jpg
index 992fe9f74..e0ada75ad 100644
Binary files a/HDL_workflow/versa_ecp5_x3_connector.jpg and b/HDL_workflow/versa_ecp5_x3_connector.jpg differ