From: Richard Earnshaw Date: Wed, 5 Jul 2017 15:32:47 +0000 (+0000) Subject: [ARM] Implement TARGET_FIXED_CONDITION_CODE_REGS X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75e2d19bc75321122cbe87bc57a5d825dd2fc6df;p=gcc.git [ARM] Implement TARGET_FIXED_CONDITION_CODE_REGS This patch implements TARGET_FIXED_CONDITION_CODE_REGS on ARM. We have two main cases to consider: in Thumb1 code there are no condition code registers, so we simply return false. For other cases we set the the first pointer to CC_REGNUM and the second to VFPCC_REGNUM iff generating hard-float code. Running the CSiBE benchmark I see a couple of cases (both in the same file) where this feature kicks in, so it's not a major change. * config/arm/arm.c (arm_fixed_condition_code_regs): New function. (TARGET_FIXED_CONDITION_CODE_REGS): Redefine. From-SVN: r250005 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 2a6a66ff592..41ee99c4af4 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2017-07-05 Richard Earnshaw + + * config/arm/arm.c (arm_fixed_condition_code_regs): New function. + (TARGET_FIXED_CONDITION_CODE_REGS): Redefine. + 2017-07-05 Richard Sandiford Alan Hayward David Sherwood diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d3a40b90252..c6101efd555 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -110,6 +110,7 @@ static void arm_print_operand_address (FILE *, machine_mode, rtx); static bool arm_print_operand_punct_valid_p (unsigned char code); static const char *fp_const_from_val (REAL_VALUE_TYPE *); static arm_cc get_arm_condition_code (rtx); +static bool arm_fixed_condition_code_regs (unsigned int *, unsigned int *); static const char *output_multi_immediate (rtx *, const char *, const char *, int, HOST_WIDE_INT); static const char *shift_op (rtx, HOST_WIDE_INT *); @@ -775,6 +776,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 2 +#undef TARGET_FIXED_CONDITION_CODE_REGS +#define TARGET_FIXED_CONDITION_CODE_REGS arm_fixed_condition_code_regs + /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; @@ -22928,6 +22932,20 @@ get_arm_condition_code (rtx comparison) return code; } +/* Implement TARGET_FIXED_CONDITION_CODE_REGS. We only have condition + code registers when not targetting Thumb1. The VFP condition register + only exists when generating hard-float code. */ +static bool +arm_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) +{ + if (!TARGET_32BIT) + return false; + + *p1 = CC_REGNUM; + *p2 = TARGET_HARD_FLOAT ? VFPCC_REGNUM : INVALID_REGNUM; + return true; +} + /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed instructions. */ void