From: Ewen McNeill <ewen@naos.co.nz>
Date: Fri, 19 Jan 2018 01:37:53 +0000 (+1100)
Subject: BIOS: Flashboot without main ram
X-Git-Tag: 24jan2021_ls180~1743^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75e7f9505a3d887b3ba23fcd4522b4d558fe4bd2;p=litex.git

BIOS: Flashboot without main ram

Modified flashboot() to skip copy to main ram if there is no main
ram, and instead execute in place out of SPI flash.  (For this to
work the linker .ld will also need to redirect references to be
inside the SPI flash mapping.)
---

diff --git a/litex/soc/software/bios/boot.c b/litex/soc/software/bios/boot.c
index edf4216a..9e5a4dc7 100644
--- a/litex/soc/software/bios/boot.c
+++ b/litex/soc/software/bios/boot.c
@@ -290,6 +290,17 @@ void netboot(void)
 #endif
 
 #ifdef FLASH_BOOT_ADDRESS
+
+/* On systems with exernal SDRAM we copy out of the SPI flash into the SDRAM
+   before running, as it is faster.  If we have no SDRAM then we have to
+   execute directly out of the SPI flash. */
+#ifdef MAIN_RAM_BASE
+#define FIRMWARE_BASE_ADDRESS MAIN_RAM_BASE
+#else
+/* Firmware code starts after (a) length and (b) CRC -- both unsigned ints */
+#define FIRMWARE_BASE_ADDRESS (FLASH_BOOT_ADDRESS + 2 * sizeof(unsigned int))
+#endif
+
 void flashboot(void)
 {
 	unsigned int *flashbase;
@@ -306,14 +317,17 @@ void flashboot(void)
 		return;
 	}
 
+#ifdef MAIN_RAM_BASE
 	printf("Loading %d bytes from flash...\n", length);
 	memcpy((void *)MAIN_RAM_BASE, flashbase, length);
-	got_crc = crc32((unsigned char *)MAIN_RAM_BASE, length);
+#endif
+
+	got_crc = crc32((unsigned char *)FIRMWARE_BASE_ADDRESS, length);
 	if(crc != got_crc) {
 		printf("CRC failed (expected %08x, got %08x)\n", crc, got_crc);
 		return;
 	}
-	boot(0, 0, 0, MAIN_RAM_BASE);
+	boot(0, 0, 0, FIRMWARE_BASE_ADDRESS);
 }
 #endif