From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Sat, 28 Mar 2015 00:59:55 +0000 (+0100)
Subject: sdram/phy/simphy: OK with DDR3
X-Git-Tag: 24jan2021_ls180~2424
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75ee8a5db9267bed42051f0ed1a6d493f68fd925;p=litex.git

sdram/phy/simphy: OK with DDR3
---

diff --git a/misoclib/mem/sdram/phy/simphy.py b/misoclib/mem/sdram/phy/simphy.py
index 1dc818e2..6ec39626 100644
--- a/misoclib/mem/sdram/phy/simphy.py
+++ b/misoclib/mem/sdram/phy/simphy.py
@@ -2,10 +2,8 @@
 # License: BSD
 
 # SDRAM simulation PHY at DFI level
-# Status:
-# - tested against software memtest with SDR/DDR/LPDDR/DDR2 with Verilator.
+# tested with SDR/DDR/DDR2/LPDDR/DDR3
 # TODO:
-# - test with DDR3
 # - add $display support to Migen and manage timing violations?
 
 from migen.fhdl.std import *