From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 29 Mar 2016 06:16:43 +0000 (-0700)
Subject: Added keep constraint to GP_SYSRESET cell
X-Git-Tag: yosys-0.7~285^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=75f0030458a6c5e37238e2437ea469ba9dfd389b;p=yosys.git

Added keep constraint to GP_SYSRESET cell
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index e22bb80cd..3acea01d2 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -105,6 +105,8 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 endmodule
 
+//keep constraint needed to prevent optimization since we have no outputs
+(* keep *)
 module GP_SYSRESET(input RST);
 	parameter RESET_MODE = "RISING";