From: Florent Kermarrec Date: Thu, 27 Jun 2019 21:20:12 +0000 (+0200) Subject: soc_core: use new way to add wisbone slave (now prefered) X-Git-Tag: 24jan2021_ls180~1139 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7618b845338072066a9d2c92774d59fbb3fd3f75;p=litex.git soc_core: use new way to add wisbone slave (now prefered) --- diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index 8f703ec8..a6592044 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -422,13 +422,12 @@ class SoCCore(Module): self._memory_regions.append((name, origin, length)) - def register_mem(self, name, address, interface, size=None): - self.add_wb_slave(mem_decoder(address), interface) - if size is not None: - self.add_memory_region(name, address, size) + def register_mem(self, name, address, interface, size=0x10000000): + self.add_wb_slave(address, interface, size) + self.add_memory_region(name, address, size) def register_rom(self, interface, rom_size=0xa000): - self.add_wb_slave(mem_decoder(self.soc_mem_map["rom"]), interface) + self.add_wb_slave(self.soc_mem_map["rom"], interface, rom_size) self.add_memory_region("rom", self.cpu_reset_address, rom_size) def get_memory_regions(self):