From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Mon, 14 Mar 2016 23:57:50 +0000 (-0700)
Subject: More RV32 tests
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7626b7f616803be5105f497aa5732a5d5cb001c6;p=riscv-tests.git

More RV32 tests
---

diff --git a/Makefile.in b/Makefile.in
index 3a47a18..9129d56 100644
--- a/Makefile.in
+++ b/Makefile.in
@@ -9,8 +9,8 @@ all: benchmarks isa
 install: all
 	install -d $(instbasedir)/share/riscv-tests/isa
 	install -d $(instbasedir)/share/riscv-tests/benchmarks
-	install -p -m 644 `find $(isa_src_dir) -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/isa
-	install -p -m 644 `find $(bmarkdir) -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/benchmarks
+	install -p -m 644 `find isa -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/isa
+	install -p -m 644 `find benchmarks -maxdepth 1 -type f` $(instbasedir)/share/riscv-tests/benchmarks
 
 benchmarks:
 	mkdir -p benchmarks
diff --git a/env b/env
index b7528b8..ef1457f 160000
--- a/env
+++ b/env
@@ -1 +1 @@
-Subproject commit b7528b89c8673bf38e5e4ec1e8f037ec2bcbee24
+Subproject commit ef1457fa7a3bf3fd58dadd0f30002828b353e573
diff --git a/isa/Makefile b/isa/Makefile
index d5b0b76..4ff1bd3 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -58,7 +58,7 @@ $$($(1)_pm_tests): $(1)-pm-%: $(1)/%.S
 $(1)_tests += $$($(1)_pm_tests)
 
 $$($(1)_v_tests): $(1)-v-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/vm.c $$< -lc -o $$@
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -lc -o $$@
 $(1)_tests += $$($(1)_v_tests)
 
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag
index 9d90b92..95943b7 100644
--- a/isa/rv32ui/Makefrag
+++ b/isa/rv32ui/Makefrag
@@ -5,7 +5,7 @@
 rv32ui_sc_tests = \
 	simple \
 	add addi \
-	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoswap_w \
+	amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \
 	and andi \
 	auipc \
 	beq bge bgeu blt bltu bne \
@@ -31,5 +31,6 @@ rv32ui_mc_tests = \
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
 rv32ui_pt_tests = $(addprefix rv32ui-pt-, $(rv32ui_sc_tests))
 rv32ui_pm_tests = $(addprefix rv32ui-pm-, $(rv32ui_mc_tests))
+rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
 
-spike_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests)
+spike32_tests += $(rv32ui_p_tests) $(rv32ui_pt_tests) $(rv32ui_pm_tests) $(rv32ui_v_tests)
diff --git a/isa/rv32ui/amoxor_w.S b/isa/rv32ui/amoxor_w.S
new file mode 100644
index 0000000..d4b775f
--- /dev/null
+++ b/isa/rv32ui/amoxor_w.S
@@ -0,0 +1,65 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# amoxor_w.S
+#-----------------------------------------------------------------------------
+#
+# Test amoxor.w instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  TEST_CASE(2, a4, 0x80000000, \
+    li a0, 0x80000000; \
+    li a1, 0xfffff800; \
+    la a3, amo_operand; \
+    sw a0, 0(a3); \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    nop; nop; nop; nop; \
+    amoxor.w	a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3))
+
+  # try again after a cache miss
+  TEST_CASE(4, a4, 0x7ffff800, \
+    li  a1, 0xc0000001; \
+    li  a4, 16384; \
+    add a5, a3, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    add a5, a5, a4; \
+    lw  x0, 0(a5); \
+    amoxor.w a4, a1, 0(a3); \
+  )
+
+  TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3))
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END
+
+  .bss
+  .align 3
+amo_operand:
+  .dword 0
+  .skip 65536