From: Ciro Santilli <ciro.santilli@arm.com>
Date: Tue, 23 Jul 2019 09:32:52 +0000 (+0100)
Subject: arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0
X-Git-Tag: v19.0.0.0~643
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76358df574d655f97aa223faf2b860a41271e920;p=gem5.git

arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0

In src/cpu/reg_class.hh, numPinnedWrites was unset because the
constructors were not well factored out.

Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index 434a69c32..a87988f14 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -2077,6 +2077,7 @@ let {{
                 case 0x1: cond = COND_VS; break;
                 case 0x2: cond = COND_GE; break;
                 case 0x3: cond = COND_GT; break;
+                default: panic("unreachable");
                 }
                 if (size == 3) {
                     return new VselD(machInst, vd, vn, vm, cond);
diff --git a/src/arch/generic/types.hh b/src/arch/generic/types.hh
index 353112913..7f9f93f42 100644
--- a/src/arch/generic/types.hh
+++ b/src/arch/generic/types.hh
@@ -32,6 +32,7 @@
 #define __ARCH_GENERIC_TYPES_HH__
 
 #include <iostream>
+#include <limits>
 
 #include "base/trace.hh"
 #include "base/types.hh"
@@ -43,6 +44,9 @@ typedef uint16_t RegIndex;
 /** Logical vector register elem index type. */
 using ElemIndex = uint16_t;
 
+/** ElemIndex value that indicates that the register is not a vector. */
+#define ILLEGAL_ELEM_INDEX std::numeric_limits<ElemIndex>::max()
+
 namespace GenericISA
 {
 
diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh
index bd49d15b0..e71e938bf 100644
--- a/src/cpu/reg_class.hh
+++ b/src/cpu/reg_class.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018 ARM Limited
+ * Copyright (c) 2016-2019 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -88,21 +88,21 @@ class RegId {
     friend struct std::hash<RegId>;
 
   public:
-    RegId() : regClass(IntRegClass), regIdx(0), elemIdx(-1) {}
+    RegId() : RegId(IntRegClass, 0) {}
+
     RegId(RegClass reg_class, RegIndex reg_idx)
-        : regClass(reg_class), regIdx(reg_idx), elemIdx(-1),
-          numPinnedWrites(0)
-    {
-        panic_if(regClass == VecElemClass,
-                "Creating vector physical index w/o element index");
-    }
+        : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
 
     explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
         : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
-          numPinnedWrites(0)
-    {
-        panic_if(regClass != VecElemClass,
-                "Creating non-vector physical index w/ element index");
+          numPinnedWrites(0) {
+        if (elemIdx == ILLEGAL_ELEM_INDEX) {
+            panic_if(regClass == VecElemClass,
+                    "Creating vector physical index w/o element index");
+        } else {
+            panic_if(regClass != VecElemClass,
+                    "Creating non-vector physical index w/ element index");
+        }
     }
 
     bool operator==(const RegId& that) const {