From: colepoirier <colepoirier@gmail.com>
Date: Sun, 7 Jun 2020 21:09:17 +0000 (-0700)
Subject: Add TrapMainStage.trap() convenience function to set trap address and PC
X-Git-Tag: div_pipeline~483
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7638ef80da2ce2dad7c70aae05836083129d370e;p=soc.git

Add TrapMainStage.trap() convenience function to set trap address and PC
to begin from on return
---

diff --git a/src/soc/fu/trap/main_stage.py b/src/soc/fu/trap/main_stage.py
index 5f4b95c9..650dc8a8 100644
--- a/src/soc/fu/trap/main_stage.py
+++ b/src/soc/fu/trap/main_stage.py
@@ -73,6 +73,17 @@ class TrapMainStage(PipeModBase):
         self.fields = DecodeFields(SignalBitRange, [self.i.ctx.op.insn])
         self.fields.create_specs()
 
+    def trap(self, m, addr, trap_addr):
+        comb  = m.d.comb
+        nia_o, srr0_o = self.o.nia, self.o.srr0
+
+        comb += nia_o.data.eq(trap_addr)
+        comb += nia_o.ok.eq(1)
+
+        comb += srr0_o.data.eq(addr) # addr to begin from on return
+        comb += srro_o.ok.eq(1)
+
+
     def ispec(self):
         return TrapInputData(self.pspec)