From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 1 Jul 2022 08:24:27 +0000 (+0100)
Subject: corrections to overview regarding predication
X-Git-Tag: opf_rfc_ls005_v1~1425
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7638f281d78a0510d698ee1681af743cca9bca7b;p=libreriscv.git

corrections to overview regarding predication
---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 639bb3057..a599b2eab 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -280,10 +280,13 @@ through the registers*.
 
 A particularly interesting case is if the destination is scalar, and the
 first few bits of the predicate are zero.  The loop proceeds to increment
-the Scalar *source* registers until the first nonzero predicate bit is
-found, whereupon a single result is computed, and *then* the loop exits.
-This therefore uses the predicate to perform Vector source indexing.
-This case was not possible without the predicate mask.
+the Vector *source* registers until the first nonzero predicate bit is
+found, whereupon a single *Scalar* result is computed, and *then* the loop
+exits.
+This in effect uses the predicate to perform *Vector source indexing*.
+This case was not possible without the predicate mask. Also, interestingly,
+the predicate mode `1<<r3` is specifically provided as a way to select
+one single entry from a Vector.
 
 If all three registers are marked as Vector then the "traditional"
 predicated Vector behaviour is provided.  Yet, just as before, all other