From: lkcl <lkcl@web>
Date: Wed, 17 Mar 2021 15:25:21 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7642638e54423507b20d875689551b281444faf9;p=libreriscv.git

---

diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index bf82f88cd..38b917b1e 100644
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -21,6 +21,7 @@ Links:
  (instruction form SVL-Form, field designations, pseudocode, SPR allocation)
 * <https://bugs.libre-soc.org/show_bug.cgi?id=615> agree sv assembly syntax
 * <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer add single/twin Predication
+* <https://bugs.libre-soc.org/show_bug.cgi?id=617> ISACaller add single/twin Predication
 
 # Code to convert
 
@@ -187,7 +188,12 @@ At the same time the `Rc=1` CR offsets normslly CR0 and CR1 for fixed and FP sca
 
 ## Single and Twin Predication
 
-* <https://bugs.libre-soc.org/show_bug.cgi?id=617> TestIssuer 
+both CR and INT predication is needed
+
+* TestIssuer <https://bugs.libre-soc.org/show_bug.cgi?id=617> 
+* ISACaller <https://bugs.libre-soc.org/show_bug.cgi?id=617>
+* power-gem5: TODO
+* Microwatt: TODO
 
 ## Element width overrides