From: Neha Agarwal <neha.agarwal@arm.com>
Date: Fri, 1 Nov 2013 15:56:21 +0000 (-0400)
Subject: mem: Fix for 100% write threshold in DRAM controller
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7645c8e611b5530b82789246b5025558f4b1a422;p=gem5.git

mem: Fix for 100% write threshold in DRAM controller

This patch fixes the controller when a write threshold of 100% is
used.  Earlier for 100% write threshold no data is written to memory
as writes never get triggered since this corner case is not
considered.
---

diff --git a/src/mem/simple_dram.cc b/src/mem/simple_dram.cc
index 9cbca6a1c..9669c7a03 100644
--- a/src/mem/simple_dram.cc
+++ b/src/mem/simple_dram.cc
@@ -563,7 +563,7 @@ SimpleDRAM::addToWriteQueue(PacketPtr pkt, unsigned int pktCount)
     accessAndRespond(pkt, frontendLatency);
 
     // If your write buffer is starting to fill up, drain it!
-    if (writeQueue.size() > writeThreshold && !stopReads){
+    if (writeQueue.size() >= writeThreshold && !stopReads){
         triggerWrites();
     }
 }