From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 24 Jun 2021 18:01:27 +0000 (+0100)
Subject: was going to set 2nd decoder up through MUX but now too complicated
X-Git-Tag: xlen-bcd~388
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76489bcf7ffbe344b832244266785fe92f0b0049;p=openpower-isa.git

was going to set 2nd decoder up through MUX but now too complicated
going to do "decoder conditions" instead
---

diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py
index 5c2b259a..79bb7412 100644
--- a/src/openpower/decoder/power_decoder2.py
+++ b/src/openpower/decoder/power_decoder2.py
@@ -832,6 +832,8 @@ class PowerDecodeSubset(Elaboratable):
         ports = self.dec.ports() + self.e.ports()
         if self.svp64_en:
             ports += self.sv_rm.ports()
+            ports.append(self.is_svp64_mode)
+            ports.append(self.use_svp64_ldst_dec )
         if self.svdecldst:
             ports += self.svdecldst.ports()
         return ports
@@ -880,20 +882,21 @@ class PowerDecodeSubset(Elaboratable):
                                            regreduce_en=self.regreduce_en)
 
         # set up submodule decoders
-        m.submodules.dec = self.dec
+        m.submodules.dec = dec = self.dec
         m.submodules.dec_rc = self.dec_rc = dec_rc = DecodeRC(self.dec)
         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec, op)
 
-        # use op from first decoder (self.dec.op) if not in SVP64-LDST mode
-        # (TODO)
-        comb += self.op.eq(self.dec.op)
-
         if self.svp64_en:
             # and SVP64 RM mode decoder
             m.submodules.sv_rm_dec = rm_dec = self.rm_dec
         if self.svdecldst:
             # and SVP64 decoder
             m.submodules.svdecldst = svdecldst = self.svdecldst
+            comb += svdecldst.raw_opcode_in.eq(dec.raw_opcode_in)
+            comb += svdecldst.bigendian.eq(dec.bigendian)
+
+        # copy op from decoder
+        comb += self.op.eq(self.dec.op)
 
         # copy instruction through...
         for i in [do.insn, dec_rc.insn_in, dec_oe.insn_in, ]:
@@ -1502,7 +1505,7 @@ def get_rdflags(e, cu):
 
 if __name__ == '__main__':
     pdecode = create_pdecode()
-    dec2 = PowerDecode2(pdecode)
+    dec2 = PowerDecode2(pdecode, svp64_en=True)
     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
     with open("dec2.il", "w") as f:
         f.write(vl)