From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Mon, 23 Oct 2006 22:46:05 +0000 (-0400)
Subject: Merge zizzer:/bk/newmem
X-Git-Tag: m5_2.0_beta2~71^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=764f27a0c9a6ba6008f60757769b52f5eee46ec1;p=gem5.git

Merge zizzer:/bk/newmem
into  zed.eecs.umich.edu:/z/hsul/work/m5/newmem

--HG--
extra : convert_revision : bb58679e101570d50c040519fb08ffbabfee7416
---

764f27a0c9a6ba6008f60757769b52f5eee46ec1
diff --cc configs/example/fs.py
index a5b8772af,3573c47ac..11b82178b
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@@ -72,25 -95,25 +95,26 @@@ class MyCache(BaseCache)
      latency = 1
      mshrs = 10
      tgts_per_mshr = 5
 +    protocol = CoherenceProtocol(protocol='moesi')
  
- # client system CPU is always simple... note this is an assignment of
+ # driver system CPU is always simple... note this is an assignment of
  # a class, not an instance.
- ClientCPUClass = AtomicSimpleCPU
- client_mem_mode = 'atomic'
+ DriveCPUClass = AtomicSimpleCPU
+ drive_mem_mode = 'atomic'
  
+ # system under test can be any of these CPUs
  if options.detailed:
-     ServerCPUClass = DerivO3CPU
-     server_mem_mode = 'timing'
+     TestCPUClass = DerivO3CPU
+     test_mem_mode = 'timing'
  elif options.timing:
-     ServerCPUClass = TimingSimpleCPU
-     server_mem_mode = 'timing'
+     TestCPUClass = TimingSimpleCPU
+     test_mem_mode = 'timing'
  else:
-     ServerCPUClass = AtomicSimpleCPU
-     server_mem_mode = 'atomic'
+     TestCPUClass = AtomicSimpleCPU
+     test_mem_mode = 'atomic'
  
- ServerCPUClass.clock = '2GHz'
- ClientCPUClass.clock = '2GHz'
+ TestCPUClass.clock = '2GHz'
+ DriveCPUClass.clock = '2GHz'
  
  if options.benchmark:
      try: