From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 23:07:55 +0000 (+0000)
Subject: use singlepipe.eq function
X-Git-Tag: ls180-24jan2020~1410
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=765fd037fc5b22e2cf4c683877407ec10e58ccdc;p=ieee754fpu.git

use singlepipe.eq function
---

diff --git a/src/add/pipeline.py b/src/add/pipeline.py
index 8389938e..39ddb809 100644
--- a/src/add/pipeline.py
+++ b/src/add/pipeline.py
@@ -10,6 +10,8 @@ from nmigen.compat.fhdl.bitcontainer import value_bits_sign
 # stages, and new members with names not starting with "_" are to be registered
 # for the next stage.
 
+from singlepipe import eq
+
 class SimplePipeline(object):
     """ Pipeline builder with auto generation of pipeline registers.
     """
@@ -50,5 +52,5 @@ class SimplePipeline(object):
         if next_stage not in self._pipeline_register_map:
             self._pipeline_register_map[next_stage] = {}
         self._pipeline_register_map[next_stage][name] = new_pipereg
-        self._pipe.sync += new_pipereg.eq(value)
+        self._pipe.sync += eq(new_pipereg, value)