From: Lisa Hsu Date: Wed, 1 Nov 2006 16:49:39 +0000 (-0500) Subject: make it so that you can do a standard switch without the caches option. this will... X-Git-Tag: m5_2.0_beta2~53^2~68^2~1 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7665be4f7066dcc65cacc010ca740a01d57e08d5;p=gem5.git make it so that you can do a standard switch without the caches option. this will have only the o3 cpu have a cache, rather than timing (warmup) + o3 have cache. --HG-- extra : convert_revision : d733de7ebb362bbd7376a0235ee7f117df2d6d37 --- diff --git a/configs/common/Simulation.py b/configs/common/Simulation.py index a2b1d84d2..a10d588fa 100644 --- a/configs/common/Simulation.py +++ b/configs/common/Simulation.py @@ -64,9 +64,16 @@ def run(options, root, testsys): switch_cpus_1[i].workload = testsys.cpu[i].workload switch_cpus[i].clock = testsys.cpu[0].clock switch_cpus_1[i].clock = testsys.cpu[0].clock + + ## add caches to the warmup timing CPU (which will be + ## xferred to O3 when you switch again) if options.caches: switch_cpus[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), L1Cache(size = '64kB')) + else: # O3 CPU must have a cache to work. + switch_cpus_1[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), + L1Cache(size = '64kB')) + switch_cpus_1[i].connectMemPorts(testsys.membus) switch_cpus[i].connectMemPorts(testsys.membus)