From: Rob Clark <robdclark@chromium.org>
Date: Wed, 9 Oct 2019 19:16:03 +0000 (-0700)
Subject: freedreno: update registers
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=766a68cdb9bff2c37ff43792056c484cfe50d75b;p=mesa.git

freedreno: update registers

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
---

diff --git a/src/freedreno/registers/a6xx.xml b/src/freedreno/registers/a6xx.xml
index b7cfecdc121..00618de0b2a 100644
--- a/src/freedreno/registers/a6xx.xml
+++ b/src/freedreno/registers/a6xx.xml
@@ -2934,7 +2934,28 @@ to upconvert to 32b float internally?
 		</reg32>
 	</array>
 
-	<reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/>
+	<reg32 offset="0xa99e" name="SP_FS_PREFETCH_CNTL">
+		<!-- unknown bits 0x7fc0 always set -->
+		<bitfield name="COUNT" low="0" high="2" type="uint"/>
+		<!-- b3 set if no other use of varyings in the shader itself.. maybe alternative to dummy bary.f? -->
+		<bitfield name="UNK3" pos="3" type="boolean"/>
+		<bitfield name="UNK4" low="4" high="11" type="a3xx_regid"/>
+	</reg32>
+	<array offset="0xa99f" name="SP_FS_PREFETCH" stride="1" length="4">
+		<reg32 offset="0" name="CMD">
+			<bitfield name="SRC" low="0" high="6" type="uint"/>
+			<bitfield name="SAMP_ID" low="7" high="10" type="uint"/>
+			<bitfield name="TEX_ID" low="11" high="15" type="uint"/>
+			<bitfield name="DST" low="16" high="21" type="a3xx_regid"/>
+			<bitfield name="WRMASK" low="22" high="25" type="hex"/>
+			<bitfield name="HALF" pos="26" type="boolean"/>
+			<!--
+			CMD seems always 0x4??  3d, textureProj, textureLod seem to
+			skip pre-fetch.. TODO test texelFetch
+			 -->
+			<bitfield name="CMD" low="27" high="31"/>
+		</reg32>
+	</array>
 
 	<reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
 
diff --git a/src/freedreno/vulkan/tu_pipeline.c b/src/freedreno/vulkan/tu_pipeline.c
index 03df9f97dfa..8a51fb05553 100644
--- a/src/freedreno/vulkan/tu_pipeline.c
+++ b/src/freedreno/vulkan/tu_pipeline.c
@@ -454,7 +454,7 @@ tu6_emit_fs_config(struct tu_cs *cs, const struct ir3_shader_variant *fs)
    if (fs->instrlen)
       sp_fs_config |= A6XX_SP_FS_CONFIG_ENABLED;
 
-   tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A99E, 1);
+   tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1);
    tu_cs_emit(cs, 0);
 
    tu_cs_emit_pkt4(cs, REG_A6XX_SP_UNKNOWN_A9A8, 1);
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_program.c b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
index 493ee67a088..084a05ea952 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_program.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_program.c
@@ -359,7 +359,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
 	/* I believe this is related to pre-dispatch texture fetch.. we probably
 	 * should't turn it on by accident:
 	 */
-	OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
+	OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1);
 	OUT_RING(ring, 0x0);
 
 	OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);