From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 9 Oct 2020 23:12:32 +0000 (-0700)
Subject: add all missing undefined cases for mul and div instructions
X-Git-Tag: convert-csv-opcode-to-binary~2026
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=766c604b7f7d448c7d492c482728c83a6fdb9881;p=libreriscv.git

add all missing undefined cases for mul and div instructions
---

diff --git a/openpower/isa/fixedarith.mdwn b/openpower/isa/fixedarith.mdwn
index 49513ed9d..47eccaead 100644
--- a/openpower/isa/fixedarith.mdwn
+++ b/openpower/isa/fixedarith.mdwn
@@ -329,7 +329,7 @@ Pseudo-code:
 
     prod[0:63] <- MULS((RA)[32:63], (RB)[32:63])
     RT[32:63] <- prod[0:31]
-    RT[0:31] <- prod[0:31]
+    RT[0:31] <- undefined(prod[0:31])
 
 Special Registers Altered:
 
@@ -367,7 +367,7 @@ Pseudo-code:
 
     prod[0:63] <- (RA)[32:63] *  (RB)[32:63]
     RT[32:63] <- prod[0:31]
-    RT[0:31] <- prod[0:31]
+    RT[0:31] <- unsigned(prod[0:31])
 
 Special Registers Altered: