From: lkcl Date: Thu, 24 Dec 2020 06:52:29 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~973 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=766e16944dc4b68b165877b6de2f6eb3509c28b0;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index a26601a0d..43898c169 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -3,7 +3,7 @@ This document provides a crash-course overview as to why SV exists, and how it works. [SIMD is known to be harmful](https://www.sigarch.org/simd-instructions-considered-harmful/): -a seductive simplicity that is easy to implement in hardware. Without predication, which is common only in 3D GPUs, SIMD only become more and more problematic with each power of two SIMD width increase. +a seductive simplicity that is easy to implement in hardware. Even with predication added, SIMD only become more and more problematic with each power of two SIMD width increase introduced through an ISA revision. Cray-style variable-length Vectors on the other hand result in stunningly elegant and small loops, with no alarmingly high setup and cleanup code, where at the hardware level the microarchitecture may execute from one element right the way through to tens of thousands at a time, yet the executable remains exactly the same. Unlike in SIMD, powers of two limitations are not involved in either the hardware nor in the assembly code.