From: Cesar Strauss <cestrauss@gmail.com>
Date: Sat, 13 Feb 2021 19:55:39 +0000 (-0300)
Subject: Check the PC value at the end of each instruction
X-Git-Tag: convert-csv-opcode-to-binary~231^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76851d5bc1ae2544821ba03ae248c22192cce93b;p=soc.git

Check the PC value at the end of each instruction

Useful for checking that the PC really points to the next instruction,
after fetching a prefixed instruction.
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index 271d7064..98d42840 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -172,6 +172,12 @@ def check_regs(dut, sim, core, test, code):
     dut.assertEqual(e_ov, ov, "ov mismatch %s" % (repr(code)))
     dut.assertEqual(e_ca, ca, "ca mismatch %s" % (repr(code)))
 
+    # Check the PC as well
+    state = core.regs.rf['state']
+    pc = yield state.r_ports['cia'].data_o
+    e_pc = sim.pc.CIA.value
+    dut.assertEqual(e_pc, pc)
+
 
 def wait_for_busy_hi(cu):
     while True: