From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Apr 2019 22:03:40 +0000 (-0700)
Subject: Add default entry to testcase
X-Git-Tag: yosys-0.9~202^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=7685469ee2f7bc038c4fd6fe98f93eb08d6fac7c;p=yosys.git

Add default entry to testcase
---

diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys
index 7ac460f13..594e62af6 100644
--- a/tests/various/muxcover.ys
+++ b/tests/various/muxcover.ys
@@ -8,12 +8,13 @@ read_verilog -formal <<EOT
                 3'b?1?: Y = B;
                 3'b1??: Y = C;
                 3'b000: Y = D;
+                default: Y = 'bx;
             endcase
     endmodule
 EOT
 
 
-## Examle usage for "pmuxtree" and "muxcover"
+## Example usage for "pmuxtree" and "muxcover"
 
 proc
 pmuxtree
@@ -35,7 +36,7 @@ read_verilog -formal <<EOT
                 3'b010: Y = B;
                 3'b100: Y = C;
                 3'b000: Y = D;
-		default: Y = 'bx;
+                default: Y = 'bx;
             endcase
     endmodule
 EOT