From: Luke Kenneth Casson Leighton Date: Fri, 28 Jun 2019 09:58:30 +0000 (+0100) Subject: mess with CSR_SV_STATE set X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76900325ef2c75e8f99dc3dd08a07b8b10a3dbba;p=riscv-isa-sim.git mess with CSR_SV_STATE set --- diff --git a/riscv/processor.cc b/riscv/processor.cc index 1b75e13..84a662d 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -517,8 +517,8 @@ reg_t processor_t::set_csr(int which, reg_t val, bool imm_mode) case CSR_SV_STATE: { // bits 0-5: mvl - 6-11: vl - 12-17: srcoffs - 18-23: destoffs - set_csr(CSR_SV_MVL, get_field(val, SV_STATE_VL )+1); - set_csr(CSR_SV_VL , get_field(val, SV_STATE_MVL)+1); + set_csr(CSR_SV_MVL, get_field(val, SV_STATE_VL )); + set_csr(CSR_SV_VL , get_field(val, SV_STATE_MVL)); set_csr(CSR_SV_SUBVL , get_field(val, SV_STATE_SUBVL)+1); // decode (and limit) src/dest VL offsets reg_t srcoffs = get_field(val, SV_STATE_SRCOFFS);