From: Cesar Strauss Date: Thu, 28 May 2020 22:49:04 +0000 (-0300) Subject: Send a one-clock "go" pulse after a configurable number of cycles X-Git-Tag: div_pipeline~757 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=769249f7c2bb546e46b5be2fbff89bd5e0b501c5;p=soc.git Send a one-clock "go" pulse after a configurable number of cycles --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 354f1d08..c26544a9 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -412,6 +412,10 @@ class CompUnitParallelTest: # during which busy_o must remain low. self.MIN_BUSY_LOW = 5 + # Number of cycles to stall until the assertion of go. + # One positive, non-zero value, for each port. + self.RD_GO_DELAY = [3, 1] + # store common data for the input operation of the processes # input operation: self.op = 0 @@ -524,12 +528,30 @@ class CompUnitParallelTest: # issue_i has risen. rd must rise on the next cycle rd = yield self.dut.rd.rel[rd_idx] assert not rd + + # stall for additional cycles. Check that rel doesn't fall on its own + for n in range(self.RD_GO_DELAY[rd_idx]): + yield + rd = yield self.dut.rd.rel[rd_idx] + assert rd + + # assert go for one cycle + yield self.dut.rd.go[rd_idx].eq(1) yield + + # rel must keep high, since go was inactive in the last cycle rd = yield self.dut.rd.rel[rd_idx] assert rd - # TODO: set dut.rd.go[idx] for one cycle + # finish the go one-clock pulse + yield self.dut.rd.go[rd_idx].eq(0) yield + + # rel must have gone low in response to go being high + # on the previous cycle + rd = yield self.dut.rd.rel[rd_idx] + assert not rd + # TODO: also when dut.rd.go is set, put the expected value into # the src_i. use dut.get_in[rd_idx] to do so