From: Eddie Hung <eddie@fpgeh.com>
Date: Tue, 6 Aug 2019 22:38:43 +0000 (-0700)
Subject: Add signed test
X-Git-Tag: working-ls180~1163^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=769c750c226cfde5efcd1f75940b25f51330d67b;p=yosys.git

Add signed test
---

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index 7e4f1765a..4257292f5 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -20,3 +20,29 @@ design -import gate -as gate
 
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
+
+##########
+
+read_verilog <<EOT
+module wreduce_sub_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+    assign o = (j >>> 4) - i;
+endmodule
+EOT
+
+hierarchy -auto-top
+proc
+design -save gold
+
+opt_expr
+wreduce
+
+dump
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
+design -stash gate
+
+design -import gold -as gold
+design -import gate -as gate
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports miter