From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Fri, 26 Jun 2020 13:35:35 +0000 (+0200)
Subject: Add signed/unsigned tests
X-Git-Tag: working-ls180~431^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2;p=yosys.git

Add signed/unsigned tests

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---

diff --git a/tests/various/signed.ys b/tests/various/signed.ys
new file mode 100644
index 000000000..2319a5da1
--- /dev/null
+++ b/tests/various/signed.ys
@@ -0,0 +1,28 @@
+# SV LRM A2.2.1
+
+read_verilog -sv <<EOT
+module test_signed();
+parameter integer signed  a = 0;
+parameter integer unsigned  b = 0;
+
+endmodule
+EOT
+
+design -reset
+read_verilog -sv <<EOT
+module test_signed();
+parameter logic signed [7:0] a = 0;
+parameter logic unsigned [7:0] b = 0;
+
+endmodule
+EOT
+
+design -reset
+logger -expect error "syntax error, unexpected TOK_INTEGER" 1
+read_verilog -sv <<EOT
+module test_signed();
+parameter signed integer a = 0;
+parameter unsigned integer b = 0;
+
+endmodule
+EOT