From: lkcl <lkcl@web>
Date: Tue, 14 Sep 2021 15:29:01 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~136
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76a67c0b877d94768df71bf232a5dda3d910511a;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index 985c192cb..c04868f93 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -7,6 +7,7 @@ Links:
 * [[sv/branches]]
 * [[openpower/isa/sprset]]
 * [[openpower/isa/condition]]
+* [[openpower/isa/comparefixed]]
 
 Condition Register Fields are only 4 bits wide: this presents some
 interesting conceptual challenges for SVP64, particularly with respect to element