From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 14 Dec 2017 01:06:39 +0000 (+0100)
Subject: Add RTLIL::Const::is_fully_ones()
X-Git-Tag: yosys-0.8~251
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76afff7ef67265b296455649c9bc6f0196aa5390;p=yosys.git

Add RTLIL::Const::is_fully_ones()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 7dc7107c1..3e873054f 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -172,6 +172,17 @@ bool RTLIL::Const::is_fully_zero() const
 	return true;
 }
 
+bool RTLIL::Const::is_fully_ones() const
+{
+	cover("kernel.rtlil.const.is_fully_ones");
+
+	for (auto bit : bits)
+		if (bit != RTLIL::State::S1)
+			return false;
+
+	return true;
+}
+
 bool RTLIL::Const::is_fully_def() const
 {
 	cover("kernel.rtlil.const.is_fully_def");
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index b33cb53a3..fc29e1e65 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -480,6 +480,7 @@ struct RTLIL::Const
 	inline const RTLIL::State &operator[](int index) const { return bits.at(index); }
 
 	bool is_fully_zero() const;
+	bool is_fully_ones() const;
 	bool is_fully_def() const;
 	bool is_fully_undef() const;