From: Yuliang Wang Date: Fri, 27 Sep 2019 08:10:30 +0000 (+0000) Subject: [AArch64][SVE2] Shift-Right Accumulate combine patterns X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76bb5af63db66ccaee0f0ae59783eda972d0db83;p=gcc.git [AArch64][SVE2] Shift-Right Accumulate combine patterns This patch adds combining support for SVE2's shift-right accumulate instructions. 2019-09-27 Yuliang Wang gcc/ * config/aarch64/aarch64-sve2.md (aarch64_sve2_sra): New combine pattern. gcc/testsuite/ * gcc.target/aarch64/sve2/shracc_1.c: New test. From-SVN: r276174 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 3d1233715a1..64cc0a95f35 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2019-09-27 Yuliang Wang + + * config/aarch64/aarch64-sve2.md (aarch64_sve2_sra): + New combine pattern. + 2019-09-26 Max Filippov * config/xtensa/xtensa.c (hwloop_optimize): Insert zero overhead diff --git a/gcc/config/aarch64/aarch64-sve2.md b/gcc/config/aarch64/aarch64-sve2.md index ee9acdcfbca..b018f5b0bc9 100644 --- a/gcc/config/aarch64/aarch64-sve2.md +++ b/gcc/config/aarch64/aarch64-sve2.md @@ -123,3 +123,22 @@ } ) +;; Unpredicated signed / unsigned shift-right accumulate. +(define_insn_and_rewrite "*aarch64_sve2_sra" + [(set (match_operand:SVE_I 0 "register_operand" "=w") + (plus:SVE_I + (unspec:SVE_I + [(match_operand 4) + (SHIFTRT:SVE_I + (match_operand:SVE_I 2 "register_operand" "w") + (match_operand:SVE_I 3 "aarch64_simd_rshift_imm" "Dr"))] + UNSPEC_PRED_X) + (match_operand:SVE_I 1 "register_operand" "0")))] + "TARGET_SVE2" + "sra\t%0., %2., #%3" + "&& !CONSTANT_P (operands[4])" + { + operands[4] = CONSTM1_RTX (mode); + } +) + diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index 82607de67fe..84670ec162b 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-09-27 Yuliang Wang + + * gcc.target/aarch64/sve2/shracc_1.c: New test. + 2019-09-26 Eric Botcazou * gcc.dg/cpp/ucs.c: Add test for new warning and adjust. diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/shracc_1.c b/gcc/testsuite/gcc.target/aarch64/sve2/shracc_1.c new file mode 100644 index 00000000000..5535c7dded6 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/shracc_1.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fdump-tree-vect-details --save-temps" } */ + +#include + +#define SHRACC(TYPE,SHIFT) \ +void __attribute__ ((noinline, noclone)) \ +f_##TYPE##_##SHIFT \ + (TYPE *restrict a, TYPE *restrict b, int n) \ +{ \ + for (int i = 0; i < n; i++) \ + a[i] += b[i] >> (SHIFT); \ +} + +SHRACC (int8_t, 5); +SHRACC (int16_t, 14); +SHRACC (int32_t, 19); +SHRACC (int64_t, 27); + +SHRACC (uint8_t, 2); +SHRACC (uint16_t, 6); +SHRACC (uint32_t, 24); +SHRACC (uint64_t, 53); + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops in function" 8 "vect" } } */ + +/* { dg-final { scan-assembler-not {\tasr\t} } } */ +/* { dg-final { scan-assembler-not {\tlsr\t} } } */ +/* { dg-final { scan-assembler-not {\tadd\t} } } */ + +/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.b, z[0-9]+\.b, #5\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.h, z[0-9]+\.h, #14\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.s, z[0-9]+\.s, #19\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tssra\tz[0-9]+\.d, z[0-9]+\.d, #27\n} 1 } } */ + +/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.b, z[0-9]+\.b, #2\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.h, z[0-9]+\.h, #6\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.s, z[0-9]+\.s, #24\n} 1 } } */ +/* { dg-final { scan-assembler-times {\tusra\tz[0-9]+\.d, z[0-9]+\.d, #53\n} 1 } } */