From: Michael Nolan <mtnolan2640@gmail.com>
Date: Sat, 16 May 2020 15:30:52 +0000 (-0400)
Subject: Add ports to ilang for test_caller.py
X-Git-Tag: div_pipeline~1136
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76bcb70b73f8b3594b9a901fe8ea4de6f2d1d426;p=soc.git

Add ports to ilang for test_caller.py
---

diff --git a/src/soc/alu/test/test_pipe_caller.py b/src/soc/alu/test/test_pipe_caller.py
index d56019b2..f42112e1 100644
--- a/src/soc/alu/test/test_pipe_caller.py
+++ b/src/soc/alu/test/test_pipe_caller.py
@@ -164,7 +164,7 @@ class ALUTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = ALUBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("pipeline.il", "w") as f:
             f.write(vl)
 
diff --git a/src/soc/branch/test/test_pipe_caller.py b/src/soc/branch/test/test_pipe_caller.py
index 335b63ed..5f7a3fdd 100644
--- a/src/soc/branch/test/test_pipe_caller.py
+++ b/src/soc/branch/test/test_pipe_caller.py
@@ -103,7 +103,7 @@ class BranchTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = BranchBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
             f.write(vl)
 
diff --git a/src/soc/cr/test/test_pipe_caller.py b/src/soc/cr/test/test_pipe_caller.py
index 1ce5b520..10ede467 100644
--- a/src/soc/cr/test/test_pipe_caller.py
+++ b/src/soc/cr/test/test_pipe_caller.py
@@ -89,7 +89,8 @@ class CRTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = CRBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        ports = alu.ports()
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
             f.write(vl)
 
diff --git a/src/soc/logical/test/test_pipe_caller.py b/src/soc/logical/test/test_pipe_caller.py
index 190a9ade..79c1e291 100644
--- a/src/soc/logical/test/test_pipe_caller.py
+++ b/src/soc/logical/test/test_pipe_caller.py
@@ -166,7 +166,7 @@ class LogicalTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = LogicalBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("logical_pipeline.il", "w") as f:
             f.write(vl)
 
diff --git a/src/soc/shift_rot/test/test_pipe_caller.py b/src/soc/shift_rot/test/test_pipe_caller.py
index 3244332b..dbd40923 100644
--- a/src/soc/shift_rot/test/test_pipe_caller.py
+++ b/src/soc/shift_rot/test/test_pipe_caller.py
@@ -183,7 +183,7 @@ class ALUTestCase(FHDLTestCase):
 
         pspec = ALUPipeSpec(id_wid=2, op_wid=get_rec_width(rec))
         alu = ShiftRotBasePipe(pspec)
-        vl = rtlil.convert(alu, ports=[])
+        vl = rtlil.convert(alu, ports=alu.ports())
         with open("pipeline.il", "w") as f:
             f.write(vl)