From: Ron Dreslinski <rdreslin@umich.edu>
Date: Fri, 7 Jul 2006 19:16:41 +0000 (-0400)
Subject: Remove hack now that ports work properly
X-Git-Tag: m5_2.0_beta1~36^2~13^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76c110d924d2adfa209ad4302af791dfe6f67946;p=gem5.git

Remove hack now that ports work properly

--HG--
extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
---

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 170c78d3a..12a47fb3e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -452,12 +452,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
 bool
 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 {
-    if (cpu->_status == DcacheWaitResponse)
-        cpu->completeDataAccess(pkt);
-    else if (cpu->_status == IcacheWaitResponse)
-        cpu->completeIfetch(pkt);
-    else
-        assert("OOPS" && 0);
+    cpu->completeIfetch(pkt);
     return true;
 }