From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 12 Feb 2017 16:42:57 +0000 (+0100)
Subject: Do not eagerly fix port widths on parameterized cells
X-Git-Tag: yosys-0.8~496
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76c4ee096bba99f787dd042bd9a6e988cf72f2dc;p=yosys.git

Do not eagerly fix port widths on parameterized cells
---

diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 4786aacaf..037fdb3b2 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -625,6 +625,9 @@ struct HierarchyPass : public Pass {
 			for (auto module : design->modules())
 			for (auto cell : module->cells())
 			{
+				if (GetSize(cell->parameters) != 0)
+					continue;
+
 				Module *m = design->module(cell->type);
 
 				if (m == nullptr)