From: lkcl <lkcl@web>
Date: Thu, 21 Apr 2022 17:54:06 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2635
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=76c677987c3a24bd67fb1449f898229b96422c63;p=libreriscv.git

---

diff --git a/openpower/sv/biginteger/analysis.mdwn b/openpower/sv/biginteger/analysis.mdwn
index 85759aecd..f44212fff 100644
--- a/openpower/sv/biginteger/analysis.mdwn
+++ b/openpower/sv/biginteger/analysis.mdwn
@@ -115,7 +115,7 @@ microarchitecture, especially at the decode phase.
 Instead, Intel, in 2012, specifically added a `mulx` instruction, allowing
 both HI and LO halves of the multiply to reach registers.  If done as a
 multiply-and-accumulate this becomes quite an expensive operation:
-3 64-Bit in, 2 64-bit registers out).
+(3 64-Bit in, 2 64-bit registers out).
 
 Long-multiplication may be performed a row at a time, starting
 with B0: